As the performance of microprocessors increase, the need to optimize operand movement and maximize the utilization of the bus becomes increasingly important. Some microprocessors employ special instructions to optimize operand movement. These instructions typically have an implied cache characteristic for the operand movement.
The use of unique operand movement instructions requires forethought and knowledge that is possibly available only at run-time. A single implied cache mode for the operand movement limits flexibility and potentially deteriorates performance. Additionally, the use of special-purpose instructions may impose an unrealistic burden on compilers, such that the special-purpose instructions are not generated.
The Motorola 68040 processor has a special instruction to implement line-size or block-size transfers. This "MOVE16" instruction transfers sixteen bytes from a source address to a destination address, where the source and destination are memory locations. The instruction takes advantage of cache read hits. No cache allocation takes place on read or write misses. Finally, cache write hits cause invalidation of matching entries.
Hewlett-Packard in its PA-RISC architecture has a similar special purpose block copy instruction. This block copy instruction provides special indications to the cache to optimize cache operation during execution of this instruction.
One problem with the approach utilized in the 68040 and PA-RISC architectures is the necessity of using a special instruction to take advantage of optimized line-sized or block-sized data transfers. A second problem involves implied cache characteristics associated with such special instructions. Unfortunately, the restrictions on such specialized instructions make it hard to utilize in more general situations. The result is that such specialized instructions are rarely generated by compilers.